Limited ATE vector memory is a growing concern nowadays with engineering teams driving towards 100% scan and ATE testing. Not only system level testing a very expensive test step, it only guarantees coverage for known functional cases. On the other hand, if the semiconductor SoC is designed with foresight, then you can get huge coverage and cost savings in a single test step.
In this post, I am going to share my learnings from my previous job where my I was to achieve high scan test coverage. Not only did I have to generate patterns that achieved high coverage, but they also had to load in the very limited ATE vector memory. I have documented the details of my learnings on my GitHub project where I also plan to upload code snippets to start with.
With the combination of techniques described here, I was able to achieve almost ~50% compression on some vectors. The compression rate is highly dependent on the type of the pattern. The concepts are universal and can be extended to any SoC tester.
This methodology is a feature of the ATE tester and can be leveraged upon by using half(channel link by 2), a quarter(channel link by 4) of the segments in the hardware. For a segment of 16, the scan channel link function can increase the scan pattern capacity by linking the memory of each channel every 16 channels. For Advantest tester, the channel link information is specified in the PXR file. When the scan channel link is used, there are restrictions on the number of scan channels that can be connected to the DUT. For instance, for a 2 channel link, only 8 channels of a segment(of total 16) can be used to connect to the DUT scan I/Os. This enables the tester to use memory from the other unused channels to link to the used channels which are connected to DUT scan I/Os, thus increasing the effective memory available for use. Besides that, the other advantage is that when we modify the pattern to enable channel link, it reduces the pattern size too.
Repeat instructions can be used in the pattern to tell the processor to apply the vector for the number of specified cycles. So contiguous identical vectors can be replaced by one repeat instruction and one vector.
A lot of times in the test patterns, there are sections wherein we only have the clock signal toggling 0101… Or 0C0C… on one or more pins. The rest of the pins have a constant value. If this is found, we can compress the pattern by replacing many tens/hundreds of vectors using a loop construct, which in ATE vector pattern looks like a ‘goto’ statement in any scripting language. For Advantest tester, this can be achieved using STI-JNI instructions and only two vectors. The STI instruction specifies N, the value specified for the operand, as the repetition count for the JNI instruction. Nested structure can be used for more complex constructs, if needed.
We can combine methods 2 and 3 in a single-pass or multi-pass logic to get larger amounts of compression. Huge benefits can be seen if implemented correctly.
For more details and code snippets for compression, please follow my SoC-ATE-Pattern-Compression project on GitHub. There, I will be uploading sample patterns, scripts with examples.
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