ATE Pattern Compression

ATE Pattern Compression

Limited ATE vector memory is a growing concern nowadays with engineering teams driving towards 100% scan and ATE testing. Not only system level testing a very expensive test step, it only guarantees coverage for known functional cases. On the other hand, if the semiconductor SoC is designed with foresight, then you can get huge coverage and cost savings in a single test step.

In this post, I am going to share my learnings from my previous job where my I was to achieve high scan test coverage. Not only did I have to generate patterns that achieved high coverage, but they also had to load in the very limited ATE vector memory. I have documented the details of my learnings on my GitHub project where I also plan to upload code snippets to start with.

With the combination of techniques described here, I was able to achieve almost ~50% compression on some vectors. The compression rate is highly dependent on the type of the pattern. The concepts are universal and can be extended to any SoC tester.

1. Scan Channel Link

2. Replace Contiguous Vectors with Repeats

3. Replace idle clock cycle with loops

4. Combine repeats with loops for additional compression

For more details and code snippets for compression, please follow my SoC-ATE-Pattern-Compression project on GitHub. There, I will be uploading sample patterns, scripts with examples.

For articles and blogs on AWS and Cloud, you can check my posts on Bizlab Technologies.

Following are my most visited posts:

AWS Command Line Interface

AWS CloudFormation Basics and Tutorial

Mocking AWS Services

Look forward to waking up every day to an interesting challenge!

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